linux nand flash驱动编写

吾爱主题阅读：161 2024-04-05 13:53:34 评论：0

很长一段时间，nand flash都是嵌入式的标配产品。nand flash价格便宜，存储量大，适用于很多的场景。现在很普及的ssd，上面的存储模块其实也是由一块一块nand flash构成的。对于linux嵌入式来说，开始uboot的加载是硬件完成的，中期的kernel加载是由uboot中的nand flash驱动完成的，而后期的rootfs加载，这就要靠kernel自己来完成了。当然，这次还是以三星s3c芯片为例进行说明。

1、nand flash驱动在什么地方，可以从drviers/mtd/Makefile来看

1	`obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/`

2、nand在mtd下面，是作为一个单独目录保存的，这时应该查看nand下的Kconfig

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 config MTD_NAND_S3C2410 tristate "NAND Flash support for Samsung S3C SoCs" depends on ARCH_S3C24XX || ARCH_S3C64XX help This enables the NAND flash controller on the S3C24xx and S3C64xx SoCs No board specific support is done by this driver, each board must advertise a platform_device for the driver to attach. config MTD_NAND_S3C2410_DEBUG bool "Samsung S3C NAND driver debug" depends on MTD_NAND_S3C2410 help Enable debugging of the S3C NAND driver config MTD_NAND_S3C2410_CLKSTOP bool "Samsung S3C NAND IDLE clock stop" depends on MTD_NAND_S3C2410 default n help Stop the clock to the NAND controller when there is no chip selected to save power. This will mean there is a small delay when the is NAND chip selected or released, but will save approximately 5mA of power when there is nothing happening.

3、不难发现，MTD_NAND_S3C2410才是那个真正的macro，尝试在Makefile找文件

1	`obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o`

4、查看s3c2410.c文件，看看基本结构构成

1 2 3 4 5 6 7 8 9 10 11 12 13 static struct platform_driver s3c24xx_nand_driver = { .probe = s3c24xx_nand_probe, . remove = s3c24xx_nand_remove, .suspend = s3c24xx_nand_suspend, .resume = s3c24xx_nand_resume, .id_table = s3c24xx_driver_ids, .driver = { .name = "s3c24xx-nand" , .of_match_table = s3c24xx_nand_dt_ids, }, }; module_platform_driver(s3c24xx_nand_driver);

5、继续分析s3c24xx_nand_probe函数

1	`s3c2410_nand_init_chip(info, nmtd, sets);`

6、之所以从中摘出了s3c2410_nand_init_chip这个函数，是因为里面进行了函数注册

类似的函数还有s3c2410_nand_update_chip函数

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 chip->write_buf = s3c2410_nand_write_buf; chip->read_buf = s3c2410_nand_read_buf; chip->select_chip = s3c2410_nand_select_chip; chip->chip_delay = 50; nand_set_controller_data(chip, nmtd); chip->options = set->options; chip->controller = &info->controller; switch (info->cpu_type) { case TYPE_S3C2410: chip->IO_ADDR_W = regs + S3C2410_NFDATA; info->sel_reg = regs + S3C2410_NFCONF; info->sel_bit = S3C2410_NFCONF_nFCE; chip->cmd_ctrl = s3c2410_nand_hwcontrol; chip->dev_ready = s3c2410_nand_devready; break ; case TYPE_S3C2440: chip->IO_ADDR_W = regs + S3C2440_NFDATA; info->sel_reg = regs + S3C2440_NFCONT; info->sel_bit = S3C2440_NFCONT_nFCE; chip->cmd_ctrl = s3c2440_nand_hwcontrol; chip->dev_ready = s3c2440_nand_devready; chip->read_buf = s3c2440_nand_read_buf; chip->write_buf = s3c2440_nand_write_buf; break ; case TYPE_S3C2412: chip->IO_ADDR_W = regs + S3C2440_NFDATA; info->sel_reg = regs + S3C2440_NFCONT; info->sel_bit = S3C2412_NFCONT_nFCE0; chip->cmd_ctrl = s3c2440_nand_hwcontrol; chip->dev_ready = s3c2412_nand_devready; if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT) dev_info(info->device, "System booted from NAND\n" ); break ; }